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EMC646SP16K 4mx16 cellularram ad-mux 1 preliminary document title 4mx16 bit cellularram ad-mux revision history revision no. history draft date remark 0.0 initial draft july 13,2007 preliminary emerging memory & logic solutions inc. 4f korea construction financial cooperative b/d, 301-1 yeon-dong, jeju-si, jeju-do, rep.of korea zip code : 690-717 tel : +82-64-740-1700 fax : +82-64-740-1 749~1750 / homepage : www.emlsi.com the attached datasheets are provided by emlsi reserve the right to change the speci fications and products. emlsi will answer t o your questions about device. if you have any questions, please contact the emlsi office.
EMC646SP16K 4mx16 cellularram ad-mux 2 preliminary x16 burst, multip lexed address/data features - 16-bit multiplexed address/data bus - sigle device supports asynchrous and burst operation - vcc, vccq voltages: 1.7v.1.95v vcc 1.7v.1.95v vccq - random access time: 70ns - burst mode read and write access: 4, 8, 16, or 32 words, or continuous burst burst wrap or sequential max clock rate: 104 mhz (tclk = 9.62ns) , 133mhz(tclk = 7.5ns) burst initial latency: 38 .5ns (4 clocks) @ 104 mhz , 37.5ns(5 clocks) @ 133 mhz taclk: 7ns @ 104 mhz , 5.5ns @ 133 mhz - low power consumption: asynchronous read: <25ma initial access, burst read: (38.5ns [4 clocks] @ 104 mhz) <35ma continuous burst read: <30ma initial access, burst read: (37.5ns [5 clocks] @ 133 mhz) <40ma continuous burst read: <35ma - low-power features on-chip temperature compen sated self refresh (tcsr) partial array refresh (par) - operating temperature range: wireless -30c to +85c options - configuration: 64mb (4 megabit x 16) - vcc core / vccq i/o voltage supply: 1.8v - timing: 70ns access - frequency: 83 mhz, 104 mhz, 133 mhz - standby current at 85c low low power : 140 a(max) low power : 160 a(max) standard : 180 a(max)
EMC646SP16K 4mx16 cellularram ad-mux 3 preliminary table of contents features....................................................................................................................... ....................................................................... 2 options................................................................................................................... ........................................................................ 2 general description....... .............. .............. .............. .............. ........... ........... ........... ............ ................................................................ 6 functional description................ ......................................................................................... ............................................................... 9 power-up initialization............................... .................................................................... ................................................................. 9 bus operating modes............................................................................................................ ............................................................. 10 asynchronous mode.................................. ....................................................................... .............................................................. 10 burst mode operation...................................................................................................... .............................................................. 12 mixed-mode operation ............................. ........................................................................ ............................................................. 15 wait operation ........................................................................................................... .................................................................. 15 lb# / ub# operation....................................................................................................... ............................................................... 15 low-power operation......... .................................................................................................. ............................................................. 16 standby mode operation ................................................................................................... ............................................................ 16 temperature compensated refresh................. .......................................................................... ................................................... 16 partial array refresh ............................. ....................................................................... ................................................................. 16 registers...................................................................................................................... ....................................................................... 17 access using cre ......................................................................................................... ............................................................... 17 software access .......................................................................................................... .................................................................. 21 bus configuration register................................................................................................ ............................................................. 23 burst length (bcr[2:0]) default = continu ous burst ............ .............. .............. .............. ............ .............................................. 24 burst wrap (bcr[3]) default = no wrap ............................................................................... .................................................... 24 drive strength (bcr[5:4]) default = outputs use half-drive strength ......... ........................................ ..................................... 25 wait polarity (bcr[10]) default = wait active high................................................................... ........................................... 26 initial access latency (bcr[14]) default = variable.................................................................. ................................................ 26 operating mode (bcr[15]) default = asynchro nous operation.......... ................. ................. ........ ........ .................................... 28 refresh configuration register............................................................................................ .......................................................... 28 device identification regi ster............................................................................................ ............................................................. 29 electrical characteristics................................ ..................................................................... ............................................................... 30 timing requirements............................................................................................................ .............................................................. 32 timing diagrams................................................................................................................ ................................................................. 36
EMC646SP16K 4mx16 cellularram ad-mux 4 preliminary list of figures figure 1: functional block diagram - 4 meg x 16 ........ .............. .............. ........... ........... ........... ........... ............................................. 6 figure 2: power-up initialization ti ming ....................................................................................... .................................................... 9 figure 3: read operation .......... ............................................................................................. ......................................................... 11 figure 4: write operation ...................................................................................................... ........................................................ 11 figure 5: burst mode read(4-word burst).................. ....................................................................... ............................................... 12 figure 6: burst mode write (4-word burst)............... ........................................................................ ............................................... 13 figure 7: refresh collision during variable-latency read operation ............................................................. ................................ 14 figure 8: wired-or wait configuration .......................................................................................... ................................................. 15 figure 9: configuration register write, asynchronous mode, followed by read arra y operation .................................... ...... 17 figure 10: configuration register write, synchronous mode, followed by read arra y operation ............ .............. .......... ........ 18 figure 11: register read, asynchronous mode, followed by read array operation .................................................. ................ 19 figure 12: register read, synchronous mode, followed by r ead array operation ................................................... ................. 20 figure 13: load configuration regist er ......................................................................................... ..................................................... 22 figure 14: read configuration regist er ......................................................................................... .................................................... 22 figure 15: bus configuration register definition ..... .......................................................................... ................................................. 23 figure 16: wait configuration during burst operation .. ......................................................................... ........................................... 26 figure 17: latency counter (variable initial latency, no refresh collision) .................................................... ................................... 27 figure 18: latency counter (fixed latency) ................ ..................................................................... .................................................. 27 figure 19: refresh configuration register mapping .... .......................................................................... ............................................. 28 figure 20: ac input / output reference waveform .. .............................................................................. ............................................ 31 figure 21: ac output load circuit .............. .............. .............. .............. .............. .............. .......... ........................................................ 31 figure 22: initialization period ... ............................................................................................ ............................................................. 36 figure 23: asynchronous read ............................... .................................................................... ...................................................... 36 figure 24: single-access burst read operation - variable la tency ............................................................... .................................. 37 figure 25: 4-word burst read operation - variable lat ency ...................................................................... ....................................... 38 figure 26: single-access burst read operation - fixed la tency .................................................................. .................................... 39 figure 27: 4-word burst read operation - fixed latency ......................................................................... ........................................ 40 figure 28: burst read terminate at end-of-row (wrap of f) ....................................................................... ....................................... 41 figure 29: burst read row boundary crossing .................................................................................... ............................................ 42 figure 30: asynchronous write ............................. ..................................................................... ..................................................... 43 figure 31: burst write operation - variable latency mo de ....................................................................... ...................................... 44 figure 32: burst write operation - fixed latency mode ... ....................................................................... ........................................ 45 figure 33: burst write terminate at end-of-row (wrap of f) ...................................................................... ...................................... 46 figure 34: burst write row boundary crossing ............. ...................................................................... ........................................... 47 figure 35: burst write followed by bu rst read .................................................................................. ............................................ 48 figure 36: asynchronous write followed by burst read . .......................................................................... .................................... 49 figure 37: burst read followed by asynchronous write . .............. .............. .............. ........... ........... .......... .................................... 50 figure 38: asynchronous write followed by asynchronous read .................................................................... ............................. 51
EMC646SP16K 4mx16 cellularram ad-mux 5 preliminary list of tables table 1: signal descriptions ................................................................................................... ...................................................... 7 table 2: bus operations ........................................................................................................ ....................................................... 8 table 3: sequence and burst length ... .............. .............. .............. .............. .............. ........... ......... .............................................. 24 table 4: drive strength ........................................................................................................ ......................................................... 25 table 5: variable latency configuration codes................................................................................... .......................................... 26 table 6: fixed latency configuration codes...................................................................................... ........................................... 27 table 7: address patterns for par(rcr[4] =1)........... ......................................................................... ......................................... 29 table 8: device identification register mapping ................................................................................ ........................................... 29 table 9: absolute maximum ratings ......................... ..................................................................... .............................................. 30 table 10: electrical characteristics and operating conditi ons .............. .............. .............. .............. .......... ..................................... 30 table 11: capacitance .......................................................................................................... .......................................................... 31 table 12: asynchronous read cycle timing requirements . .............. .............. ........... ........... ............ ........... ............................... 32 table 13: burst read cycle timing requirements ........ .............. .............. ............ ........... ........... ........... ....................................... 33 table 14: asynchronous write cycle timing requirements . .............. .............. ........... ........... ............ .......... ............................... 34 table 15: burst write cycle timing requirements ................................................................................ ...................................... 35 table 16: initialization timing parameters ..................................................................................... ................................................. 36
EMC646SP16K 4mx16 cellularram ad-mux 6 preliminary general description 64m cellularram products are high-speed, cmos pseudo-stati c random access memory developed for low-power, portable applications. the 64mb cellularram device has a dram core organized as 4 meg x 16 bits. these devices are a variation of the industry-standard flash control interface, with a multiplexed address/data bus . the multiplexed address and data functionality dramatically reduce the required signal coun t, and increases read/write bandwidth. fo r seamless operation on a burst flash bus , 64m cellularram products incorporate a transparent self refresh mechanism. the hidden refres h requires no additional support from t he system memory controller and has no significant impact on device read/write performance. two us er accessible control registers define device operation. the bus configurat ion register (bcr) defines how the 64m cellu larram device interacts with the system memory bus and is nearly identical to its counterpart on burst mode flash devices. the refresh co nfiguration register (rcr) is used to control how refresh is performed on the dram array. these regist ers are automatically loaded with default settings during power -up and can be updated anytime during normal operation. special attention has been focused on standby current consumption during self refresh. 64m cellularram products include two mechanisms to mi nimize standby current. partial array refresh (par) enables the system to limit refresh to only that part of the dram array that contains esse ntial data. temperature compensated self refresh (tcsr) uses an onchip sensor to adjust the refres h rate to match the device temperature-the refresh rate decreases at lower temperatur es to minimize current consumption during standby. the system conf igurable refresh mechanisms are accessed through the rcr. this 64m cellularram specification defines the industry-standard cellular ram1.5 x16 a/d mux feature set established by the cellularram workgroup. it includes support for both variable and fixed late ncy, with three output-device dr ive-strength settings, a variety of wrap options, and a device id register (didr). figure 1: funtional bl ock diagram - 4 meg x 16 note: functional block diagrams illustrate simplified device oper ation. see pin descriptions; bu s operations table; and timing diagrams for detailed information. control logic clk ce# we# oe# adv# cre lb# ub# wait address decode logic refresh configuration register (rcr) device id register (didr) bus configuration register (bcr) 4,096k x 16 dram memory array input output mux and buffers a/dq[7:0] a/dq[15:8] a[21:16] external internal
EMC646SP16K 4mx16 cellularram ad-mux 7 preliminary table 1: signal descriptions note: 1. when using asynchronous mode exclusively, clk can be tied to vssq or vccq. wait should be ignored during asynchronous mod e operations. symbol type descriptions a[21:16] input address inputs: inputs for addresses during read and write operations. addresses are internally latched during read and write cycles. the address lines are also used to define the value to be loaded into the bcr or the rcr. clk (note1) input clock: synchronizes the memory to the system oper ating frequency dur ing synchronous operations. when configured for synchronous operation, the address is latched on the first rising clk edge when adv# is active. clk must be static (high or low) during asynchronous access read and write operations when burst mode is enabled. adv# (note1) input address valid: indiates that a valid address is pres ent on the address inputs. addresses are latched on the rising edge of adv# during asynchronous read and write operations. cre input control register enable: when cre is high, write operations load the rcr or bcr, and read operations access the rcr, bcr, or didr. ce# input chip enable: activates the device when low. when ce# is high, the device is disabled and goes into standby mode. oe# input output enable: enables the output buffers when lo w. when oe# is high, the output buffers are disabled. we# input write enable: determines if a given cycle is a write cycle. if we# is low, the cycle is a write to either a configuration register or to the memory array. lb# input lower byte enable. dq[7:0] ub# input upper byte enable. dq[15:8] a/dq[15:0] input/output address/data i/os: these pins are a multiplexed addr ess/data bus. as inputs for address, these pins behave as a[15:0]. a[0] is the lsb of the 16-bit wo rd address within the cellularram device. address, rcr, and bcr values are loaded with adv# low. da ta is input or output when adv# is high. wait (note1) output wait: provides data-valid feedback during burst read and write operations. wait is used to arbitrate collisions between refresh and read/write operations. wait is also asserted at the end of row unless wrapping within the burst length. wait should be i gnored during asynchronous operations. wait is high-z when ce# is high. rfu - reserved for future use. vcc supply device power supply: (1.70v.1.95v) power supply for device core operation. vccq supply i/o power supply: (1.70v.1.95v) power supply for input/output buffers. vss supply vss must be c onnected to ground. vssq supply vssq must be connected to ground.
EMC646SP16K 4mx16 cellularram ad-mux 8 preliminary table 2: bus operations note: 1. with burst mode enabled, clk must be static(high or low) duri ng asynchronous reads and asynchr onous writes and to achieve st andby power during standby mode. 2. the wait polarity is configured through the bus configuration register (bcr[10]). 3. when lb# and ub# are in select mode (low), dq[15:0] are enabled. when only lb# is in select mode, dq[7:0] are enabled. when only ub# is in the select mode, dq[15:8] are enabled. 4. the device will consume active power in this mode whenever addresses are changed. 5. when the device is in standby mode, address inputs and data i nputs/outputs are internally isolated from any external influen ce. 6. vin = vccq or 0v; all device pins must be static (unswitched) in order to achieve standby current. 7. when the bcr is configured for sync mode, sync read and write, and async write are supported by emlsi 8. burst mode operation is initialized through the bus configuration register (bcr[15]). 9. initial cycle. following cycles are the same as burst continue . ce# must stay low for the equivalent of a single-word burst (as indicated by wait). asynchfonous mode bcr[15]=1 power clk adv# ce# oe# we# cre ub#/ lb# wait 2 dq[15:0] notes read active x l l h l l low-z data out 4 write active x l x l l l high-z data in 4 standby standby h or l x h x x l x high-z high-z 5, 6 no operation idle x x l x x l x low-z x 4, 6 configuration register write active x l h l h x low-z high-z configuration register read active x l l h h l low-z config. reg.out burst mode bcr[15]=0 power clk adv# ce# oe# we# cre ub#/ lb# wait dq[15:0] notes async read active h or l l l h l l low-z data out 4, 7 async write active h or l l x l l l low-z data in 4 standby standby h or l x h x x l x high-z high-z 5, 6 no operation idle h or l x l x x l x low-z x 4, 6 initial burst read active l l x h l l low-z address 4, 8 initial burst write active l l h l l x low-z address 4, 8 burst continue active h l x x x l low-z data out or data in 4, 8 configuration register write active l l h l h x low-z high-z 8, 9 configuration register read active l l l h h l low-z config. reg.out 8, 9
EMC646SP16K 4mx16 cellularram ad-mux 9 preliminary funtional description in general, 64m cellularram devices are high-density alternat ives to sram and pseudo sram products, popular in low-power, portable applications. the 64mb device contains a 67,108,864-bit dram core, organized as 4,194,304 addresses by 16 bits.the dev ice implement a multiplexed address/data bus. this multiplexed configuration supports greate r bandwidth through the x16 data bus, y et still reduces the required signal count. the 64m cellularram bus in terface supports both asynchro nous and burst mode transfers. power-up initialization 64m cellularram products include an on-chip voltage sensor used to launch the power-up initializ ation process. initialization w ill configure the bcr and the rcr with their def ault settings. vcc and vccq must be applied simultaneously. when they reach a stabl e level at or above 1.7v, the device will require 150 s to complete its se lf-initialization proc ess. until the end of t pu, ce# should track vccq and remain high. when initialization is comp lete, the device is ready for normal operation. figure 2: power-up initialization timing vcc vccq vcc=1.7v t pu device initialization device ready for normal operation
EMC646SP16K 4mx16 cellularram ad-mux 10 preliminary bus operating modes 64m celluarram products incorporate a burst mode interface found on flash products targ eting low-power, wireless applications. this bus interface supports asynchronous and burst mode read and write tran sfers. the specific interface supported is defined by the value loaded into the bcr. asynchronous mode asynchronous mode uses the industry- standar d sram control signals (ce#, adv#, oe#, we#, and lb#/ub#). read operations(fig- ure 3 on page 11) are initiated by bringing ce#, adv#, and lb#/ ub# low while keeping oe# and we # high, and driving the address onto the a/dq bus. adv# is take n high to capture the address, an d oe# is taken low. valid data will be driven out of the i/os a fter the specified access time has elapsed. write operations(figure 4 on page 11) occur when ce#, adv#, we#, and lb#/ub# are driven low. with the address on the a/dq bus. adv# is taken high to capt ure the address, then the write da ta is driven onto the bus. d ur- ing asynchronous write operations, the oe# level is a ?don't care,? and we# will override oe#; however, oe# must be high while the address is driven onto the a/dq bus. t he data to be written is latched on the risi ng edge of ce#, we#, ub#, or lb# (whichev er occurs first). during asynchronous operations with burst mode enabl ed, the clk input must be held static(high or low). wait wi ll be driven during asynchronous reads, and its state should be ignored. we# low time must be limited to tcem.
EMC646SP16K 4mx16 cellularram ad-mux 11 preliminary figure 3: read operation figure 4: write operation don?t care ce# oe# lb#/ub# a/dq[15:0] we# high-z address valid valid data adv# a[21:16] address valid don?t care ce# oe# lb#/ub# a/dq[15:0] we# address valid adv# undefined valid data t cem a[21:16] address valid
EMC646SP16K 4mx16 cellularram ad-mux 12 preliminary burst mode operation burst mode operations enable high-speed synchronous read and write operations. burst operations consist of a multi-clock sequence that must be performed in an ordered fashion. after ce # goes low, the address to access is latched on the rising edge of the next clock that adv# is low. during this first clock rising edge, we# indicates whether the operation is going to be a read (we # = high, figure 5) or write (we# = low, figure 6 on page 13). figure 5: burst mode read (4-word burst) note: non-default bcr settings for burst mode read (4-word burst): fixed or variable latency; latency code two (three clocks); wait ac tive low; wait asserted during delay. diagram in the figure above is representative of variabl e latency with no refresh collision or fixed-latency access. clk latency code 2(3 clocks) don?t care undefined read burst identified (we# = high) read burst identified (we# = high) ce# a[21:16] adv# oe# we# lb#/ub# wait a/dq[15:0] d0 address address address address d1 d2 d3
EMC646SP16K 4mx16 cellularram ad-mux 13 preliminary figure 6: burst mode writ e (4-word burst, oe# high) note: non-default bcr settings for burst mode write (4-word burst): fixed or variable latency; latency code two (three clocks); wait active low; wait asserted during delay. the size of a burst can be specified in the bcr either as a fi xed length or continuous. fixed- length bursts consist of four, ei ght, sixteen, or thirty-two words. continuous bursts have the ability to start at a specif ied address and burst to the end of the address. it goes back to the first address and continues to burst when continuous bursts meet the end of address. the latency count stored in the bcr defines the number of clock cycles that elapse before the initial data value is transferred between the processor and cellularram device. the initial latency for read operations can be configured as fixed or variabl e (write operations always use fixed latency). variable latency allows the cellularram to be configured for minimum lat ency at high clock frequencies, but the controller must monitor wait to detect any conflict with refresh cycles. fixed latency outputs the first data word after the worst-case ac cess delay, including allowance for refresh collisions. the in itial latency time and clock speed determine the latency count setting. fi xed latency is used when the controller cannot monitor wait. fixed latency also pr ovides improved performance at lower clock frequencies. the wait output asserts when a burst is initiated, and de-asserts to indicate when data is to be transferred into (or out of ) the memory. wait will again be asserted at the boundary of the row, unless wrapping within the burst length. with wrap off, the cellularram device will res tore the previous row?s data and access the next row, wait will be de-asserted, and the burs t can continue across the row boundary(see figeure 29 on page 42 for a read, figure 34 on page 47 for a write). if the burst is to terminate at the row boundary, ce# must go high within 2 clocks of the last data (see figure 28 on page 41). ce# must go high before any clock edge following the last word of a defined-length burst write(see figure 31 and 32 on pag es 44 and 45). the ce# low time is limited by refresh considerations. ce# mu st not stay low longer than t cem . if a burst suspension will cause ce# to remain low for longer than t cem , ce# should be taken high and the burst rest arted with a new ce# low/adv# low cycle. clk latency code 2(3 clocks) don?t care write burst identified (we# = low) write burst identified (we# = low) ce# a[21:16] adv# we# lb#/ub# wait a/dq[15:0] address address address address d0 d1 d2 d3
EMC646SP16K 4mx16 cellularram ad-mux 14 preliminary figure 7: refresh collision during variable-latency read operation note: non-default bcr settings for refresh collis ion during variable-latency read operation: latency code two (three clocks); wait acti ve low; wait asserted during delay. clk don?t care undefined a[21:16] adv# oe# we# lb#/ub# a/dq[15:0] v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol d0 d1 d2 d3 additional wait states inserted to allow refresh completion. valid address valid address v oh v ol ce# v ih v il wait v oh v ol high-z
EMC646SP16K 4mx16 cellularram ad-mux 15 preliminary mixed-mode operation the device supports a combination of synchronous read and asyn chronous write operations when the bcr is configured for synchronous operation. the asynchronous write operations require that the clock (clk) remain static (high or low) during the entire sequence. the adv# signal can be used to latch the tar get address. ce# can remain low when the device is transitioning between mixed-mode operations with fixed latency en abled; however, the ce# low time must not exceed t cem . mixed-mode operation facilitates a seamless interface to legacy bu rst mode flash memory contro llers. see figure 36 on page 49 for the ?asynchronous write followed by burst read? timing diagram. wait operation the wait output on a cellularram device is typically connected to a shared, system-level wait signal(see figure 8). the shared wait signal is used by the processor to coordinate transa ctions with multiple memories on the synchronous bus. figure 8: wired or wait configuration when a burst read or write operation has been initiated, wait goe s active to indicate that the cellularram device requires addi - tional time before data can be transferred. for burst read operati ons, wait will remain active until valid data is output from the device. for burst write operations, wait will indicate to the memory controller when data will be accepted into the cellularram device. when wait transitions to an inactive state, the data burst will progress on successive clock edges. during a burst cycle, ce# must remain assert ed until the first data is va lid. bringing ce# high during this in itial latency may cause data corruption. when using variable initial access latency (bcr[14] = 0), the wa it output performs an arbitration role for burst read operation s launched while an on-chip refresh is in progress. if a collision occurs, wait is asserted for additional clock cycles until the refresh has completed(see figure 7 on page 14). when the refresh operation has completed, the burst read operation will continue normally. wait is also asserted when a continuous read or write burst crosses a row boundary. the wait assertion allows time for the new row to be accessed. wait will be asserted after oe# goes low during asynchronous re ad operations. wait will be high-z during asynchronous write operations. wait should be ignored du ring all asynchronous operations. by using fixed initial latency (bcr[14] = 1), this cellularram de vice can be used in burst mode without monitoring the wait sig nal. how- ever, wait can still be used to determine when valid data is availa ble at the start of the burst and at the end of the row. if wait is not monitored, the controller must properly terminate all burst accesses at row boundaries on its own. lb#/ub# operation the lb# enable and ub# enable signals support byte-wide data writes. during write operations, any disabled bytes will not be transferred to the ram array and the internal value will remain unchanged. during an asynchronous write cycle, the data to be w ritten is latched on the rising edge of ce#, we#, lb#, or ub#, whichever occurs first. lb# and ub# must be low during read cycles. whe n both the lb# and ub# are disabled (high) during an operation, the device will disable t he data bus from receiving or transmitti ng data. although the device will seem to be deselected, it re mains in an active mode as long as ce# remains low. ready processor cellularram wait wait other device external pull-up pull-down resistor wait other device
EMC646SP16K 4mx16 cellularram ad-mux 16 preliminary low-power operation standby mode operation during standby, the device current consumption is reduced to t he level necessary to perform the dram refresh operation. standby operation occurs when ce# is high. the device will enter a reduced power state upon completion of a read or write operation, or when the address and control inputs remain static for an ex tended period of time. this mode will continue until a change occurs to the address or control inputs. temperature compensated refresh temperature compensated self refr esh (tcsr) allows for adequate refresh at differ ent temperatures. this cellularram device incl udes an on-chip temperature sensor that automa tically adjusts the refresh rate according to the operating temperature. the device co ntinually monitors the temperature to select an appropriate self-refresh rate. partial a rray refresh partial array refresh (par) restricts refresh operation to a port ion of the total memory array. this feature enables the device to reduce standby current by refreshing only that part of the memory arra y required by the host system. the refresh optio ns are full arra y, one-half array, one-quarter array, one-eighth array, or none of the array. the mapping of these partitions can start at either the begin ning or the end of the address map(see table 7 on page 29). read and write operations to address ranges receiving refresh will not be affec ted. data stored in addresses not receiving refresh will become corrupt ed. when re-enabling additional portions of the array, the ne w portions are available immediately upon writing to the rcr.
EMC646SP16K 4mx16 cellularram ad-mux 17 preliminary registers two user-accessible configuration registers define the device operat ion. the bus configuration regi ster (bcr) defines how the c ellular- ram interacts with the system memory bus an d is nearly identical to its counterpart on burst mo de flash devices. the refresh configuration register (rcr) is used to c ontrol how refresh is performed on the dram array. these registers are automatically l oaded with default settings during power-up, and can be updated any time the devices are operating in a standby state. a didr provide s information on the device manufacturer, cellularram generation, and the specific device configurat ion. the didr is read-only. access using cre the registers can be accessed using either a synchronous or an a synchronous operation when the c ontrol register enable (cre) in put is high(see figure 9 through 12 on pages 17 through 20) . when cre is low, a read or write operation will access the memory array. the configuration register values are written via addresses a[21: 16] and a/dq[15:0]. in an a synchronous write, the value s are latched into the configuration register on the rising edge of adv#, ce#, or we#, whichever occurs first; lb# and ub# are ?don?t care?. the bcr is accessed when a[19:18] are 10b; the rcr is accessed wh en a[19:18] are 00b. the didr is read when a[19:18] are 01b. for reads, address inputs other than a[19:18] are ?don?t care ?, and register bits 15:0 are ou tput on dq[15:0]. immediately afte r a configuration register read or write operation is perf ormed, reading the memory array is highly recommended. figure 9: configuration regist er write, asynchronous mode, followed by read array operation note: a[19:18] = 00b to load rcr, and 10b to load bcr. don?t care a[21:16] adv# oe# we# lb#/ub# a/dq[15:0] opcode address a[19:18] 1 (except a[19:18]) cre write address bus value t wp t vp t avs t avs address select control register t avh t avh t cph ce# t cw to control register opcode address valid data initiate control register access
EMC646SP16K 4mx16 cellularram ad-mux 18 preliminary figure 10: configuration register write, synchronous mode , followed by read array operation note: 1. nondefault bcr settings for synchronous mode configuration register write followed by read array operation: latency code 2 (3 clocks), wait active low, wait asserted during delay. 2. a[19:18] = 00b to load rcr, and 10b to load bcr. 3. ce# must remain low to complete a burst-of-one write. wait must be monitored ; additional wait cycles caused by refresh collisions require a correspondi ng number of additional ce# low cycles. don?t care a[21:16] adv# oe# we# a/dq[15:0] opcode a[19:18] 2 (except a[19:18]) cre clk wait t cbph latch control register address t sp t sp t hd t hd t khtl high-z ce# t csp latch control register value lb#/ub# opcode address address address valid data high-z note3 t sp t hd t sp t hd
EMC646SP16K 4mx16 cellularram ad-mux 19 preliminary figure 11: register read, asynchronous mode , followed by read array operation note: a[19:18] = 00b to read rcr, 1 0b to read bcr, and 01b to read didr. ce# adv# oe# we# lb#/ub# a/dq[15:0] a[19:18] 1 address cre initiate register access t vp t avs t avs valid cr don?t care undefined t aa t aa t aadv t cph t hz t ohz t bhz t co t oe t olz t ba t avh select register a[21:16] address (except a[19:18]) address valid data t cph t avh
EMC646SP16K 4mx16 cellularram ad-mux 20 preliminary figure 12: register read, synchronous mode , followed by read array operation note: 1. nondefault bcr settings for synchronous mode register read followed by read array operation: latency code 2 (3 clocks), wait active low, wait asserted during delay. 2. a[19:18] = 00b to read rcr, 10b to read bcr, and 01b to read didr. 3. ce# must remain low to complete a burst-of-one read. wait must be monitored; additional wait cycles caused by refresh collis ions require a corresponding number of additional ce# low cycles. a[21:16] oe# we# a[19:18] 2 (except a[19:18]) cre clk latch control register address t sp t sp t hd t hd latch control register value lb#/ub# address address adv# t cbph ce# t csp t sp t hd note3 a/dq[15:0] valid data valid cr address wait t khtl high-z high-z don?t care undefined t aba t boe t hz t ohz t olz t hd t aclk t koh t sp
EMC646SP16K 4mx16 cellularram ad-mux 21 preliminary software access software access of the registers uses a sequence of asynchron ous read and asynchronous write operations. the contents of the configuration registers can be modified and all re gisters can be read using the software sequence. the configuration registers are loaded using a four-step sequence consisti ng of two asynchronous read operations followed by tw o asynchronous write operations (see figure 13 on page 22). the r ead sequence is virtually identical except that an asynchronous read is performed during the fourth operation (see figure 14 on page 22). the address used during all read and write operations is the highest address of the cellularram device being accessed (3fffffh); the contents of this address are not changed by usin g this sequence. the data value presented during the third operation (write) in th e sequence defines whether the bcr, rcr, or the didr is to be accessed. if the data is 0000h, the sequence will access the rcr; if the data is 0001h, the sequence will access the bcr; if th e data is 0002h, the sequence will access the didr. this value must be vali d at the falling edge of we#. during the fourth operation, dq[ 15:0] transfer data in to or out of bits 15:0 of the registers. the use of the software sequence does not af fect the ability to perform the standard (cre-controlled) method of loading the configuration registers. however, the software nature of this access mechanism eliminates the need for cre. if the software mec hanism is used, cre can simply be tied to vss. the port line often used for cre cont rol purposes is no longer required.
EMC646SP16K 4mx16 cellularram ad-mux 22 preliminary figure 13: load configuration register note: if the data at the falling edge of we# is not 0000h, 0001h or 0002h, it is possible that the data stored at the highest memory location will be altered. figure 14: read configuration register note: if the data at the falling edge of we# is not 0000h, 0001h or 0002h, it is possible that the data stored at the highest memory location will be altered. a[21:16] ce# oe# we# lb#/ub# a/dq[15:0] rcr : 0000h bcr : 0001h don?t care cr value in address (max) address (max) address (max) address (max) address (max) address (max) address (max) address (max) xxxx xxxx 0ns (min); note 1 read read write write adv# ce# oe# we# lb#/ub# rcr : 0000h bcr : 0001h don?t care cr value out address (max) address (max) address (max) address (max) address (max) address (max) address (max) address (max) xxxx xxxx 0ns (min); note 1 read read write read adv# a[21:16] a/dq[15:0] didr : 0002h
EMC646SP16K 4mx16 cellularram ad-mux 23 preliminary bus configuration register the bcr defines how the cellularram device interacts with the system memory bus. figure 15 describes the control bits in the bc r. at power-up, the bcr is set to 9d1f h. the bcr is accessed with cre hi gh and a[19:18] = 10b, or through the register access softwar e sequence with a/dq = 0001h on the third cycle. figure 15: bus configuration register definition note: 1. burst wrap and length apply to both read and write operations. 2. reserved bits must be set to zero. reserved bits not se t to zero will affect device functionallity. bcr[15:0] will be read back as written. a [21:20] a [19:18] a [17:16] a/dq 15 a/dq 14 a/dq [13:11] a/dq 10 a/dq 9 a/dq 8 a/dq 7 a/dq 6 a/dq [5:4] a/dq 3 a/dq [2:0] 21-20 19-18 17-16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved register select reserved operating mode initial latency latency counter wait polarity reserved wait configuration(wc) reserved reserved drive strength burst wrap(bw) burst length(bl) bcr[14] initial access latency bcr[3] burst wrap (note 1) 0 variable (default) 0 burst wraps within the burst length 1 fixed 1 burst no wrap (default) bcr[5] bcr[4] drive strength bcr[13] bcr[12] bcr[11] latency counter 00 full 0 0 0 code 8 0 1 1/2 (default) 0 0 1 code 1 - reserved 1 0 1/4 0 1 0 code 2 1 1 reserved 0 1 1 code 3 (default) 1 0 0 code 4 1 0 1 code 5 bcr[8] wait configuration 1 1 0 code 6 0 asserted during delay 1 1 1 code 7 - reserved 1 asserted one data cycle before delay (default) bcr[10] wait polarity 0 active low 1 active high (default) bcr[15] operating mode 0 synchronous burst access mode bcr[2] bcr[1] bcr[0] burst length (note 1) 1 asynchronous access mode (default) 0 0 1 4 words 01 0 8 words bcr[19] bcr[18] register select 01 1 16 words 0 0 select rcr 10 0 32 words 1 0 select bcr 11 1 continuous burst (default) 0 1 select didr others reserved all must be set to ?0? must be set to ?0? must be set to ?0? must be set to ?0? must be set to ?0?
EMC646SP16K 4mx16 cellularram ad-mux 24 preliminary burst length (bcr[2:0]) default = continuous burst burst lengths define the number of words the device outputs during burst read and write operations. the device supports a burst length of 4, 8, 16, or 32 words. the device can also be set in continuous burst mode where data is output sequentially without regard to address boundaries; the internal address wraps to 0 00000h if the device is read past the last address. burst wrap (bcr[3]) default = no wrap the burst-wrap option determines if a 4, 8, 16, or 32 word read or write burst wraps within the burst length, or steps through sequential addresses. if the wr ap option is not enabled, the device accesses da ta from sequential addre sses without regard to a ddress boundaries; the internal address wrap to 000000h if the device is read past the last address. table 3: sequence and burst length burst wrap starting address 4 word burst length 8 word burst length 16 word burst length 32 word burst length continuous burst bcr[3] wrap decimal linear linear linear linear linear 0yes 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2 ... 29-30-31 0-1-2-3-4-5-6-... 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 1-2-3 ... 30-31-0 1-2-3-4-5-6-7-... 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 2-3-4 ... 31-0-1 2-3-4-5-6-7-8-... 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 3-4-5 ... 0-1-2 3-4-5-6-7-8-9-... 4 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 4-5-6 ... 1-2-3 4-5-6-7-8-9-10-... 5 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 5-6-7 ... 2-3-4 5-6-7-8-9-10-11-... 6 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 6-7-8 ... 3-4-5 6-7-8-9-10-11-12-... 7 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 7-8-9 ... 4-5-6 7-8-9-10-11-12-13-... ... ... ... ... 14 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 14-15-16-...-11-12-13 14-15-16-17-18-19-20-... 15 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17...-12-13-14 15-16-17-18-19-20-21-... ... ... ... 30 30-31-0-...-27-28-29 30-31-32-33-34-... 31 31-0-1-... -28-29-30 31-32-33-34-35-... 1no 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 0-1-2-...-29-30-31 0-1-2-3-4-5-6-... 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16 1-2-3-...-30-31-32 1-2-3-4-5-6-7-... 2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17 2-3-4-...-31-32-33 2-3-4-5-6-7-8-... 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18 3-4-5-...-32-33-34 3-4-5-6-7-8-9-... 4 4-5-6-7-8-9-10-11 4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19 4-5-6-...-33-34-35 4-5-6-7-8-9-10-... 5 5-6-7-8-9-10-11-12 5-6-7-8-9-10-11-12-13-14-15-16-17-18-19-20 5-6-7-...-34-35-36 5-6-7-8-9-10-11-... 6 6-7-8-9-10-11-12-13 6-7-8-9-10-11-12-13-14-15-16-17-18-19-20-21 6-7-8-...-35-36-37 6-7-8-9-10-11-12-... 7 7-8-9-10-11-12-13-14 7-8-9-10-11-12-13-14-15-16-17-18-19-20-21-22 7-8-9-...-36-37-38 7-8-9-10-11-12-13-... ... ... ... ... 14 14-15-16-17-18-...-23-24-25-26-27-28-29 14-15-16-...43-44-45 14-15-16-17-18-19-20-... 15 15-16-17-18-19-...-24-25-26-27-28-29-30 15-16-17-...-44-45-46 15-16-17-18-19-20-21-... ... ... ... 30 30-31-32-...-59-60-61 30-31-32-33-34-35-36-... 31 31-32-33-...-60-61-62 31-32-33-34-35-36-37-...
EMC646SP16K 4mx16 cellularram ad-mux 25 preliminary drive strength (bcr[5:4] ) default = outputs use half-drive strength the output driver strength can be altered to full, one-half, or one-quarter strength to adjust for different data bus loading s cenarios. the reduced-strength options are intended for stacked chip (flash + cellularram) environments when there is a dedicated memory bus. the reduced-drive-strength option minimizes the noise generated on th e data bus during read operations. full output drive strength should be selected when using a discrete cellularram device in a more heavily loaded data bus environment . outputs are configured at h alf- drive strength during testing. see table 4 for additional information. table 4: drive strength bcr[5] bcr[4] drive strength impedance typ ( ? ) use recommendation 0 0 full 25~30 cl = 30pf to 50pf 01 1/2 (default) 50 cl = 15pf to 30pf 104 mhz at light load 1 0 1/4 100 cl = 15pf or lower 11 reserved
EMC646SP16K 4mx16 cellularram ad-mux 26 preliminary wait configuration (bcr[8]) default = wait transitions one clock before data valid/invalid the wait configuration bit is used to det ermine when wait transitions between the asse rted and the de-asserted state with respe ct to valid data presented on the data bus. the memory controller will use the wait signal to coordinate data transfer during synchro nous read and write operations. when bcr[8] = 0, data will be valid or invalid on the clock edge immediately after wait transitions to the de-asserted or asserted state, respectively. when bcr[8] = 1, the wait signal transitions one clock period prior to the data bu s going valid or invalid(see figure 16). wait polarity (bcr[10]) default = wait active high the wait polarity bit indicates whether an asserted wait output should be high or low. this bit will determine whether the wait signal requires a pull-up or pull-down resi stor to maintain the de-asserted state. figure 16: wait configuration during burst operation note: non-default bcr setting: wait active low. latency counter (bcr[13:11]) default = three clock latency the latency counter bits determine how many clocks occur between the beginning of a r ead or write operati on and the first data value transferred. for allowable latency codes, see table 5 and 6 on pages 26 and 27, respectively, and figure 17 and 18 in pa ge 27, respctively. initial access latency (bcr[14]) default = variable variable initial access latency out puts data after the number of clocks set by the latency counter. however, wait must be monit ored to detect delays caused by collisions with refresh operations. fixed initial access latency outputs the first data at a consistent time that allows for worst-case refresh collisions. the latency counter mu st be configured to match the in itial latency and the clock fre quency. it is not necessary to monitor wait with fixed in itial latency. th e burst begins after the number of clock cycles configured by the l atency counter(see table 6 on page 27 and figure 18 on page 27). table 5: variable latency configuration codes note: 1. latency is the number of clock cycl es from the initiation of a burst operation until data appears. data is transferred on the next clock cycle. bcr[13:11] latency configuration code latency 1 max input clk frequency (mhz) normal refresh collision 133 104 83 010 2 (3 clocks) 2 4 66(15ns) 66(15ns) 52(19.2ns) 011 3 (4 clocks)-default 3 6 104(9.62ns) 104(9.62ns) 83(12ns) 100 4 (5 clocks) 4 8 133(7.5ns) - - others reserved - - - - - clk a/dq[15:0] d1 d2 d3 end of row don?t care initial latency d0 wait bcr[8] = 0 data valid in current cycle wait bcr[8] = 1 data valid in next cycle
EMC646SP16K 4mx16 cellularram ad-mux 27 preliminary figure 17: latency counter (variable in itial latency, no refresh collision ) table 6: fixed latency configuration codes figure 18: latency counter (fixed latency) bcr[13:11] latency configuration code latency count (n) max input clk frequency (mhz) normal 133 104 83 010 2 (3 clocks) 2 33(30ns) 33(30ns) 33(30ns) 011 3 (4 clocks)-default 3 52 (19.2ns) 52(19.2ns) 52(19.2ns) 100 4 (5 clocks) 4 66(15ns) 66(15ns) 66(15ns) 101 5 (6 clocks) 5 75(13.3ns) 75(13.3ns) 75(13.3ns) 110 6 (7 clocks) 6 104(9.62ns) 104(9.62ns) 83(12ns) 000 8 (9 clocks) 8 133(7.5ns) - - others reserved -- - - - v ih v il v ih v il v ih v il v ih v il clk a[21:16] adv# code 2 code 3 (default) v ih v il a/dq[15:0] a/dq[15:0] d0 d1 d2 d3 d4 d5 d6 d7 d7 d6 d5 d4 d3 d2 d1 d0 code 4 v ih v il a/dq[15:0] d6 d5 d4 d3 d2 d1 d0 valid address valid address valid address valid address don?t care undefined v ih v il v ih v il v ih v il v ih v il clk a[21:16] adv# a/dq[15:0] a/dq[15:0] t aa cycle n n-1 cycles t aadv t co (read) (write) ce# v oh v ol v oh v ol valid output valid output valid output valid output valid output valid input valid input valid input valid input valid input don?t care undefined burst identified (adv# = low) t aclk t sp t hd valid address valid address input valid
EMC646SP16K 4mx16 cellularram ad-mux 28 preliminary operating mode (bcr[15]) default = asynchronous operation the operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation. refresh configuration register the refresh configuration register (rcr) defines how the cellularram device perfor ms its transparent self refresh. altering the refresh parameters can dramatically reduce current consumption during st andby mode. figure 19 describes the control bits used in the rc r. at power-up, the rcr is set to 0010h. the rcr is accessed with cre high and a[19:18] = 00b; or throu gh the register access softwar e sequence with a/dq = 0000h on the third cycle. figure 19: refresh configuration register mapping note: 1. reserved bits must be set to zero. reserved bits not se t to zero will affect device func tionality. rcr[15:0] will be r ead back as written. a[21:20] a[19:18] a[17:16] a/dq [15:7] a/dq 6 a/dq 5 a/dq 4 a/dq 3 a/dq 2 a/dq 1 a/dq 0 21~20 19-18 17-16 15~7 6 5 4 3 2 1 0 reserved register select reserved reserved ignored reserved par rcr[19] rcr[18] register select rcr[2] rcr[1] rcr[0] refresh coverage 0 0 select rcr 0 0 0 full array (default) 1 0 select bcr 0 0 1 bottom 1/2 array 0 1 select didr 0 1 0 bottom 1/4 array 0 1 1 bottom 1/8 array 1 0 0 none of array 1 0 1 top 1/2 array 1 1 0 top 1/4 array 1 1 1 top 1/8 array all must be set to ?0? all must be set to ?0? setting is ignored must be set to ?0? (default 001b)
EMC646SP16K 4mx16 cellularram ad-mux 29 preliminary partial array refresh (rcr[2:0] default = full array refresh) the par bits restrict refresh operation to a portion of the total memory array. this feature allows the dev ice to reduce standb y current by refreshing only that part of the memory array required by the ho st system. the refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. the mapping of these partitions can st art at either the beginning or the end of the address map(see table 7 and table 8). table 7: address patterns for par (rcr[4] = 1) device identification register the didr provides information on the device manufacturer, cellularram generation, and the specific device configuration. table 8 describes the bit fields in the didr. this register is read-onl y. the didr is accessed with cre hi gh and a[19:18] = 01b, or thr ough the register access software sequence with a/dq = 0002h on the third cycle. table 8: device identification register mapping rcr[2] rcr[1] rcr[0] active section address space size density 0 0 0 full die 000000h-3fffffh 4 meg x 16 64mb 0 0 1 one-half die 000000h-1fffffh 2 meg x 16 32mb 0 1 0 one-quarter of die 000000h-0fffffh 1 meg x 16 16mb 0 1 1 one-eighth of die 000000h-07ffffh 512 k x 16 8mb 1 0 0 none of die 0 0 meg x 16 0mb 1 0 1 one-half of die 200000h-3fffffh 2 meg x 16 32mb 1 1 0 one-quarter of die 300000h-3fffffh 1 meg x 16 16mb 1 1 1 one-eighth of die 380000h-3fffffh 512 k x 16 8mb bit field didr[15] didr[14:11] didr[10:8] didr[7:5] didr[4:0] field name row length device version device density cellularram generation vendor id length bit setting version bit setting density bit setting generation bit setting vendor bit setting options 256 words 1b 1st 0000b 64mb 010b cr 1.5 010b emlsi 01010b 2nd 0001b ... ...
EMC646SP16K 4mx16 cellularram ad-mux 30 preliminary electrical characteristics table 9: absolute maximum ratings stresses greater than those listed may c ause permanent damage to the device. this is a stress rating only, and functional opera tion of the device at these or any other conditions above those indicated in the operational se ctions of this specification is not implied. exposure to abs olute maximum rating conditions for extended peri ods may affect reliability. table 10: electrical characteris tics and operating conditions wireless temperature (-30c < t c < +85c) note: 1. input signals may overshoot to vccq + 1.0v for periods less than 2ns during transitions. 2. input signals may undershoot to vss - 1.0v for periods less than 2ns during transitions. 3. bcr[5:4] = 01b (default setting of one-half drive strength). 4. this parameter is specified with the outputs disabled to avoi d external loading effects. the user must add the current requi red to drive output capacitance expected in the actual system. 5. isb (max) values measured with par set to full array and at +85c. in order to achieve low standby current, all inputs must be driven to either vccq or vss. isb might be slightly higher fo r up to 500ms after power-up, or when entering standby mode. 6. isb (typ) is the average isb at 25c and vcc = vccq = 1.8v. this parameter is verified during characterization, and is not 1 00% tested. parameter rating voltage to any pin except vcc, vccq relative to vss -0.3v to vccq + 0.3v voltage on vcc supply relative to vss -0.2v to +2.45v voltage on vccq supply relative to vss -0.2v to +2.45v storage temperature (plastic) -55c to +150c operating temperature (case) wireless -30c to +85c soldering temperature and time: 10s (solder ball only) +260c description conditions symbol min max unit notes supply voltage v cc 1.7 1.95 v i/o supply voltage v ccq 1.7 1.95 v input high voltage v ih v ccq - 0.4 v ccq + 0.2 v1 input low voltage v il -0.20 0.4 v 2 output high voltage i oh = -0.2ma v oh 0.80 v ccq v3 output low voltage i ol = +0.2ma v ol 0.20 v ccq v3 input leakage current v in = 0 to v ccq i li 1 a output leakage current oe# = v ih or chip disabled i lo 1 a operating current conditions symbol typ max unit notes asynchronous random read/write v in = v ccq or 0v chip enabled, i out = 0 i cc 1 70ns 25 ma 4 initial access, burst read/write i cc 2 133mhz 40 ma 4 104mhz 35 ma 83mhz 30 ma continuous burst read i cc 3r 133mhz 35 ma 4 104mhz 30 ma 83mhz 25 ma continuous burst write i cc 3w 133mhz 40 ma 4 104mhz 35 ma 83mhz 30 ma standby current v in = v ccq or 0v, ce# = v ccq isb standard tbd 180 a 5, 6 low power 160 a low-low power 140 a
EMC646SP16K 4mx16 cellularram ad-mux 31 preliminary table 11: capacitance note: 1. these parameters are verified in dev ice characterization and are not 100% tested. figure 20: ac input/outp ut reference waveform note: 1. ac test inputs are driven at vccq for a logic 1 and vssq for a logic 0. input rise and fall times (10% to 90%) <1.6ns. 2. input timing begins at vccq/2. 3. output timing ends at vccq/2. figure 21: ac output load circuit note: all tests are performed with the outputs configured for default setting of half drive strength (bcr[5:4] = 01b). description conditions symbol min max unit notes input capacitance tc = = +25c; f = 1 mhz; v in = 0v c in 2.0 6 pf 1 input/output capacitance(a/ dq) c io 3.0 6.5 pf 1 vccq vssq input 1 vccq/2 2 vccq/2 3 tes t p o i n ts output dut te s t p o i n ts 50 ? 30pf vccq/2
EMC646SP16K 4mx16 cellularram ad-mux 32 preliminary timing requirements table 12: asynchronous read cycle timing requirements all tests performed with outputs configured for default setting of half drive st rength, (bcr[5:4] = 01b). note: 1. the high-z timings measure a 100mv transition from either v oh or v ol toward vccq/2. 2. the low-z timings measure a 100mv transition aw ay from the high-z (vccq/2) level toward either v oh or v ol . parameter symbol min max unit notes address access time t aa 70 ns adv# access time t aadv 70 ns address hold from adv# high t avh 2ns address setup to adv# high t avs 5ns lb#/ub# access time t ba 70 ns lb#/ub# disable to dq high-z output t bhz 7ns1 chip select access time t co 70 ns ce# low to adv# high t cvs 7ns chip disable to dq and wait high-z output t hz 7ns1 output enable to valid output t oe 20 ns oe# low to wait valid t oew 17.5ns output disable to dq high-z output t ohz 7ns1 output enable to low-z output t olz 3ns2 adv# pulse width t vp 5ns
EMC646SP16K 4mx16 cellularram ad-mux 33 preliminary table 13: burst read cycle timing requirements all tests performed with outputs configured for default setting of half drive st rength, (bcr[5:4] = 01b). note: 1. a refresh opportunity must be provided every t cem . a refresh opportunity is satisfied by either of the following two conditions: a) clocked ce# high, or b) ce# high for longer than 15ns. 2. the high-z timings measure a 100mv transition from either v oh or v ol toward vccq/2. 3. the low-z timings measure a 100mv transition aw ay from the high-z (vccq/2) level toward either v oh or v ol . parameter symbol 133mhz 104mhz 83mhz unit notes min max min max min max address access time (fixed latency) t aa 70 70 70 ns adv# access time (fixed latency) t aadv 70 70 70 ns burst to read access time (variable latency) t aba 35.5 35.9 45 ns clk to output delay t aclk 5.5 7 9 ns address hold from adv# high(fixed latency) t avh 222ns burst oe# low to output delay t boe 20 20 20 ns ce# high between subsequent burst or mixed mode operations t cbph 556ns1 maximum ce# pulse width t cem 444 s 1 clk period t clk 7.5 9.62 12 ns chip select access time (fixed latency) t co 70 70 70 ns ce# setup time to active clk edge t csp 2.5 3 4 ns hold time from active clk edge t hd 1.5 2 2 ns chip disable to dq and wait high-z output t hz 777ns2 clk rise or fall time t khkl 1.2 1.6 1.8 ns clk to wait valid t khtl 5.5 7 9 ns output hold from clk t koh 222ns clk high or low time t kp 334ns output disable to dq high-z output t ohz 777ns2 output enable to low-z output t olz 333ns3 setup time to active clk edge t sp 233ns
EMC646SP16K 4mx16 cellularram ad-mux 34 preliminary table 14: asynchronous write cycle timing requirements note: 1. the high-z timings measure a 100mv transition from either v oh or v ol toward vccq/2. 2. we# low time must be limited to t cem (4 s). parameter symbol min max unit notes address and adv# low setup time to we# low t as 0ns address hold from adv# going high t avh 2ns address setup to adv# going high t avs 5ns address valid to end of write t aw 70 ns lb#/ub# select to end of write t bw 70 ns ce# high between subsequent async operations t cph 5ns ce# low to adv# high t cvs 7ns chip enable to end of write t cw 70 ns data hold from write time t dh 0ns data write setup time t dw 20 ns chip disable to wait high-z output t hz 7ns1 adv# pulse width t vp 5ns adv# setup to end of write t vs 70 ns write to dq high-z output t whz 7ns1 write pulse width t wp 45 ns 2 write recovery time t wr 0ns
EMC646SP16K 4mx16 cellularram ad-mux 35 preliminary table 15: burst write cycle timing requirements note: 1. t as required if t csp > 20ns. 2. a refresh opportunity must be provided every t cem . a refresh opportunity is satisfied by either of the following two conditions: a) clocked ce# high, or b) ce# high for longer than 15ns. 3. the high-z timings measure a 100mv transition from either v oh or v ol toward vccq/2. parameter symbol 133mhz 104mhz 83mhz unit notes min max min max min max address and adv# low setup time to we# low t as 000ns1 address hold from adv# high(fixed latency) t avh 222ns ce# high between subsequent burst or mixed mode operations t cbph 556ns2 maximum ce# pulse width t cem 444 s 2 clock period t clk 7.5 9.62 12 ns ce# setup to clk active edge t csp 2.5 3 4 ns hold time from active clk edge t hd 1.5 2 2 ns chip disable to wait high-z output t hz 777ns3 clk rise or fall time t khkl 1.2 1.6 1.8 ns clock to wait valid t khtl 5.5 7 9 ns output hold from clk t koh 222ns clk high or low time t kp 334ns setup time to activate clk edge t sp 233ns
EMC646SP16K 4mx16 cellularram ad-mux 36 preliminary timing diagrams figure 22: initialization period table 16: initialization timing parameters figure 23: asynchronous read parameter symbol min max unit initialization period (required before normal operations) t pu 150 s vcc, vccq = 1.7v vcc (min) device ready for normal operation t pu a[21:16] valid address adv# ce# lb#/ub# oe# a/dq[15:0] valid output wait high-z high-z t aa t avs t avh v ih v il v ih v il t vp t cvs t aadv t hz v ih v il v ih v il t co t ba v ih v il we# v ih v il t bhz t ohz v ih v il v oh v ol v oh v ol t oe t olz t aa t avs t avh t oew t hz valid address don?t care undefined
EMC646SP16K 4mx16 cellularram ad-mux 37 preliminary figure 24: single-access burst read operation - variable latency 1. non-default bcr settings: latency code two (three clo cks); wait active low; wait asserted during delay. clk adv# ce# oe# wait high-z a/dq[15:0] high-z t hd t csp a[21:16] valid address t khkl t sp t hd t sp t hd t sp t hd valid output lb#/ub# t hz t ohz t olz t boe t sp t khtl high-z read burst identified (we# = high) v ih v il we# v ih v il v ih v il v ih v il v ih v il v oh v ol t aba high-z t clk v il v ih v ih v il v ih v il t kp t koh t aclk valid v oh v ol address t khtl t sp t hd t koh t hd t cem t kp don?t care undefined
EMC646SP16K 4mx16 cellularram ad-mux 38 preliminary figure 25: 4-word burst read operation - variable latency notes : 1. non-default bcr settings: latency code two (three clocks); wait active low; wait asserted during delay. 2. wait will remain de-asserted even if ce# remains low past the end of the defined burst length. 3. a/dq[15:0] will output undefined data if ce# remains low past the end of the defined burst length. valid output valid output clk adv# ce# oe# wait high-z a/dq[15:0] high-z t hd t csp a[21:16] valid address t clk t sp t hd t sp t hd t sp t hd valid lb#/ub# t koh t cbph t hz t boe t sp t khtl high-z read burst identified (we# = high) v ih v il we# v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t khkl t kp t ohz output valid output t aba t cem t kp t hd valid address v oh v ol t hd t sp t olz t aclk t khtl t koh note 2 note 3 v ih v il don?t care undefined
EMC646SP16K 4mx16 cellularram ad-mux 39 preliminary figure 26: single-access burst read operation - fixed latency 1. non-default bcr settings: fixed laten cy; latency code four (five clocks); wait active low; wait asserted during delay. clk adv# ce# oe# wait high-z a/dq[15:0] high-z t hd t csp a[21:16] valid address t clk t sp t sp t sp valid output ub#/lb# t koh t hz t ohz t olz t boe t sp t aclk high-z read burst identified (we# = high) v ih v il we# v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t avh t kp t kp t hd v ih v il t sp t avh v oh v ol t khtl t khtl t koh t hd t aa t aadv t cem t co t khkl t hd t hd valid address don?t care undefined
EMC646SP16K 4mx16 cellularram ad-mux 40 preliminary figure 27: 4-word burst read operation - fixed latency notes : 1. non-default bcr settings: fixed latency; latency code two (three clocks); wait active low; wait asserted during delay. 2. wait will remain de-asserted even if ce# remains low past the end of the defined burst length. 3. a/dq[15:0] will output undefined data if ce# remains low past the end of the defined burst length. valid output valid output clk adv# ce# oe# wait high-z a/dq[15:0] high-z t hd t csp a[21:16] valid address t clk t sp t sp t hd t sp t hd valid ub#/lb# t cbph t hz t boe t sp t aclk high-z read burst identified (we# = high) v ih v il we# v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t khkl t kp t kp t ohz output valid output t cem t aa t aadv t co t olz t avh v ih v il t sp t avh v oh v ol t koh t hd t koh t khtl t khtl note 3 note 2 valid address don?t care undefined
EMC646SP16K 4mx16 cellularram ad-mux 41 preliminary figure 28: burst read terminate at end-of-row (wrap off) notes : 1. non-default bcr settings for burst read at end of row : fixe d or variable latency, wait active low; wait asserted during del ay. 2. for burst reads, ce# must go high before the second clk after the wait period begins ( befor the second clk after wait asser ts with bcr[8]=0, or before the third clk after wait asserts with bcr[8]=1 ). clk adv# ce# oe# wait a/dq[15:0] a[21:16] t clk ub#/lb# t hz high-z v ih v il we# v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t khtl t hz note 2 v oh v ol t koh end of row t hd t csp valid output valid output don?t care undefined
EMC646SP16K 4mx16 cellularram ad-mux 42 preliminary figure 29: burst read row boundary crossing note: 1. nondefault bcr settings for burst read at end of row : fixed or variable latency, wait active low, wait asserted during dela y. (shown as solid line) 2. wait will be assert for lc or lc + 1 cycles for variables latency, or lc cycles for fixed latency. clk adv# ce# oe# wait a/dq[15:0] a[21:16] t clk ub#/lb# v ih v il we# v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol valid output valid output valid out valid output note 2 t kthl t koh end of row t kthl t koh t sp t hd don?t care
EMC646SP16K 4mx16 cellularram ad-mux 43 preliminary figure 30: asynchronous write a[21:16] valid address adv# ce# t cw ub#/lb# t bw we# high-z oe# t wp t dw t dh v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh t aw v ol t as t avs t vs t vp t aw t as valid input a/dq[15:0] wait t avh valid address t avs t avh t cvs t as don?t care
EMC646SP16K 4mx16 cellularram ad-mux 44 preliminary figure 31: burst write operat ion - variable latency mode note: 1. nondefault bcr settings for burst write operation in variable latency mode: latency code 2 (3 clocks), wait active low, wait asserted during delay, burst length 4, burst wrap enabled. 2. wait asserts for lc cycles for both fixed and variable latency. lc = latency code (bcr[13:11]). 3. t as required if t csp > 20ns. 4. ce# must go high before any clock edge following the last word of a defined-length burst. clk adv# ce# oe# wait a/dq[15:0] t hd t csp a[21:16] valid address t clk t sp t hd t sp t hd t sp t hd d1 ub#/lb# t hd t cbph t hz t sp write burst identified (we# = low) v ih v il we# v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t khkl t kp t cem t as 3 t hd note 2 t khtl d2 d3 d0 t sp t as 3 valid address note4 t koh t sp t hd high-z high-z t kp t khtl t as 3 don?t care
EMC646SP16K 4mx16 cellularram ad-mux 45 preliminary figure 32: burst write operation - fixed latency mode note: 1. nondefault bcr settings for burst write operation in fixed late ncy mode: fixed latency, latenc y code 2(3 clocks), wait activ e low, wait asserted during delay, burst length 4, burst wrap enabled. 2. wait asserts for lc cycles for both fixed and variable latency. lc = latency code (bcr[13:11]). 3. t as required if t csp > 20ns. 4. ce# must go high before any clock edge following the last word of a defined-length burst. clk adv# ce# oe# t hd t csp a[21:16] valid address t clk t sp t sp t hd t sp t hd ub#/lb# t cbph t sp write burst identified (we# = low) v ih v il we# v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t khkl t kp t cem t as 3 t hd t as 3 note 4 wait high-z a/dq[15:0] t sp d1 t hd note2 t khtl d2 d3 d0 t sp valid address t koh t avh high-z t khtl t hz t as 3 t kp t avh don?t care
EMC646SP16K 4mx16 cellularram ad-mux 46 preliminary figure 33: burst write termina te at end-of-row (wrap off) note: 1. nondefault bcr settings for burst write at end of row: fixed or variable latency, wait active low, wait asserted during dela y. (shown as solid line) 2. for burst writes, ce# must go high before the second clk af ter the wait period begins(befor the second clk after wait assert s with bcr[8]=0, or before the third clk after wait asserts with bcr[8]=1). clk adv# ce# oe# wait a[21:16] t clk ub#/lb# t hz high-z v ih v il we# v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t koh t hz note 2 a/dq[15:0] valid intput intput valid t khtl end of row t hd t csp t sp t hd don?t care
EMC646SP16K 4mx16 cellularram ad-mux 47 preliminary figure 34: burst write row boundary crossing note: 1. nondefault bcr settings for burst write at end of row : fixed or variable latency, wait active low, wait asserted during de lay. (shown as solid line) 2. wait will be assert for lc or lc + 1 cycles for variables latency, or lc cycles for fixed latency. clk adv# ce# oe# wait a/dq[15:0] a[21:16] t clk ub#/lb# v ih v il we# v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il valid input valid input valid output note 2 t kthl t koh end of row t kthl t koh valid output t sp t hd valid input don?t care
EMC646SP16K 4mx16 cellularram ad-mux 48 preliminary figure 35: burst write followed by burst read note: 1. nondefault bcr settings for burst write followed by burst read: fixed or variable latency, latency code 2 (3 clocks), wait a ctive low, wait asserted during delay. 2. a refresh opportunity must be provided every t cem. a refresh opportunity is satisfied by either of the following two conditions: a) clocked ce# high, or b) ce# high for longer than 15ns. valid address clk adv# ce# oe# wait a/dq[15:0] a[21:16] ub#/lb# v ih v il we# v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol note 2 valid address t clk valid output t csp t sp t hd valid address t sp t hd t sp t hd t csp t sp t hd t sp t hd valid output valid output valid output t sp t hd t cbph t hd t ohz t hd t boe t aclk t koh t sp t hd d0 d1 d2 d3 valid address v oh v ol t sp t hd high-z high-z t sp t sp t hd don?t care undefined
EMC646SP16K 4mx16 cellularram ad-mux 49 preliminary figure 36: asynchronous write followed by burst read note: 1. nondefault bcr settings for asynchronous write, with adv# lo w, followed by burst read: fixed or variable latency, latency co de 2 (3 clocks), wait active low, wait asserted during delay. 2. when the divice is transitioning between asynchronous and variable-latency burst operations, ce# must go high. ce# can stay low when the device is transitioning to fixed-latency burst reads. a refres h opportunity must be provided every t cem. a refresh opportunity is satisfied by either of the following two conditions: a) clo cked ce# high, or b) ce# high for longer than 15ns. clk adv# ce# oe# wait a/dq[15:0] a[21:16] ub#/lb# v ih v il we# v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol note 2 valid address valid output valid output valid output valid output t cbph t ohz t boe t aclk t koh valid address data t clk t sp t hd t sp t hd t avs t vp t cw t csp t wc t bw t sp t sp t hd t as t wp t dw t avh valid address t as t avs t dh t avh valid address t sp t hd v oh v ol high-z t khtl t hd don?t care undefined
EMC646SP16K 4mx16 cellularram ad-mux 50 preliminary figure 37: burst read follow ed by asynchronous write notes: 1. nondefault bcr settings for burst read followed by asynchronous wr ite using adv#: fixed or variable latency, latency code 2 (3 clocks), wait active low, wait asserted during delay. 2. when the device is transitioning betw een asynchronous and variable-latency burst operations, ce# must go high. ce# can stay low when the device is transitioning from fixed-latency bu rst reads; asynchronous operation begins at the falling edge of adv# . a refresh opportunity must be provided every t cem. a refresh opportunity is satisfied by either of the following two conditions: a) clocked ce# high, or b) ce# high for longer than 15ns. clk adv# ce# oe# wait a/dq[15:0] t hd t csp a[21:16] valid address t clk t sp t hd t sp t hd t sp t hd valid output ub#/lb# t aclk t koh t hz t ohz t olz t boe t sp t khtl read burst identified (we# = high) v ih v il we# v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il valid address t wph valid input v ih v il t vs t cbph note 2 t as t wp t bw t dh t dw t avs t vp t aw t cw t as t hd valid address v oh v ol valid address t sp t hd t koh high-z t khtl t avh t avs t avh high-z t as don?t care undefined
EMC646SP16K 4mx16 cellularram ad-mux 51 preliminary figure 38: asynchronous write followed by asynchronous read note: 1. when configured for synchronous mode (bcr[15] = 0), ce# must remain high for at least 5ns ( t cph) to schedule the appropriate refresh interval. otherwise, t cph is only required after ce#-controlled writes. adv# ce# oe# wait a/dq[15:0] a[21:16] ub#/lb# v ih v il we# v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il note 1 valid address t cph valid address t cw t ba t wp t aa v alid output t hz t co t oe t ohz t bhz t avs t vp t avh t as t aw t bw t as t cvs t wr t vp t olz valid address valid input valid address v oh v ol t oez t avs t avh t avs t avh t aw t ds t dh t avs t avh high-z t aadv t vs t hz t as t aa t cvs don?t care undefined
EMC646SP16K 4mx16 cellularram ad-mux 52 preliminary em x xx x x x xx x x x - xx xx memory function guide 1. emlsi memory 2. device type 3. density 5. technology 6. operating voltage 8. version 9. option 11. speed 7. organization 4. function 12. power 10. pkg 1. memory component 2. device type 6 ---------------------- low power sram 7 ---------------------- stram c ---------------------- cellularram 3. density 4 ----------------------- 4m 8 ----------------------- 8m 16 --------------------- 16m 32 --------------------- 32m 64 --------------------- 64m 28 --------------------- 128m 4. function 2 ----multiplexed async. 3-----demultiplexed async. with page mode 4-----demultiplexed async. with direct dpd 5-----multiplexed sync. 6-----optiona l mux/demuxed sync. 5. technology s ----------------------- single transistor & trench cell 6. operating voltage v ----------------------- 3.3v u ----------------------- 3.0v s ----------------------- 2.5v r ----------------------- 2.0v p ----------------------- 1.8v l ----------------------- 1.5v 7. organization 8 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit 8. version blank ----------------- mother die a ----------------------- 2?nd generation b ----------------------- 3?rd generation c ----------------------- 4?th generation d ----------------------- 5?th generation 9. option blank ---- no optional mode h ----------- demultiplexed with dpd j ------------ demultiplexed with dpd & rbc k ------------ multiplexed with rbc l ------------ multiplexed with dpd & rbc 10. package blank ---------------------- wafer s ---------------------- 32 stsop1 t ---------------------- 32 tsop1 u ---------------------- 44 tsop2 p ---------------------- 48 fpbga z ---------------------- 52 fpbga y ---------------------- 54 fpbga v ---------------------- 90 fpbga 11. speed (@async.) 45 ---------------------- 45ns 55 ---------------------- 55ns 70 ---------------------- 70ns 85 ---------------------- 85ns 90 ---------------------- 90ns 10 --------------------- 100ns 12 --------------------- 120ns 12. power ll ---------------------- low low power lf ---------------------- low low power (pb-free&green) l ---------------------- low power

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